中文名: 赛灵思逻辑设计环境ISE 9.1i 英文名: Xilinx ISE 9.1i

Xilinx ISE 9.1i

Xilinx ISE 9.1 终于于2007.3月释放。业界最完整的可编程逻辑设计解决方案，用于实现最优性能、功率管理、降低成本和提高生产率。 ISE 9.1i 利用新 SmartCompile 技术，来帮助用户在更少的时间内实现业内最快速的 FPGA 性能！ISE™ 9.1i 是 Xilinx 最新推出的业内领先的设计工具，其性能比竞争解决方案平均快 30%。 新 SmartCompile 技术让您能够更快、更轻松地实现时序收敛。

赛灵思公司（Xilinx, Inc）2007推出业界应用最广泛的集成软件环境（ISE™）设计套件的最新版本ISE 9.1i。新版本专门为满足业界当前面临的主要设计挑战而优化，这些挑战包括时序收敛、设计人员生产力和设计功耗。除了运行速度提高2.5倍以外，ISE 9.1i还新采用了SmartCompile 技术，因而可在确保设计中未变更部分实施结果的同时，将硬件实现的速度再提高多达6倍。同时，ISE 9.1i 还优化了其最新65nm Virtex™-5 平台独特的ExpressFabric™技术，可提供比竞争对手的解决方案平均高出30%的性能指标。对于功耗敏感的应用， ISE 9.1i还可将动态功耗平均降低10%。

这一革命性的技术得益于赛灵思Synplicity超高容量时序收敛工作组（Xilinx-Synplicity Ultra High-Capacity Timing Closure Task Force）的工作成果。 该技术提供了业界领先的生产力提升能力，可保证最快的时序收敛路径，并且优化了赛灵思领先的Virtex™ 系列和Spartan™-3 新一代 FPGA器件产品的功耗和性能。

“对于少许设计更改来说，特别是在设计周期的后期，快速的设计实施速度和可预测的时序结果极为重要。”领先的定制汽车系统供应商德国Harmon/Becker 汽车系统有限公司负责制图平台的高级技术专家Jochen Frensch说：“对于较小的设计变更，XST (Xilinx Synthesis Technology) 的综合技术可保留设计未改变部分的名称，而SmartGuide技术在实施过程中可保持高达99%的设计实现不变，因此我们可以发现实施的运行速度越来越快。ISE 9.1i中新采用的SmartGuide技术提供了巨大的优势。”

ISE 9.1i 提供：

性能 - 比现有竞争解决方案平均快 30%

生产率 - 推出了新 SmartCompile 技术

功耗 - 动态功耗平均降低 10%

性能

比现有竞争解决方案平均快 30%

ISE 9.1i 仍居于性能领先地位。

无需进行布局规划即可实现时序收敛

*改善的预布线延迟估计使得上游工具能够优化真正的关键路径。

*利用 Virtex™-5 对角互联来实现延迟优化

*支持 6 LUT，从而改善了性能、功耗和利用率

*减少 LUT 数量 → 减少布线和逻辑电平 → 提高性能和降低功耗

*物理综合优化

ISE 9.1i 设计工具内的特性基于 ISE Fmax 技术的性能，专门用于为基于 Virtex-5 的、高密度、高性能设计提供无可比拟的性能和时序收敛结果。 ISE 9.1i 集成式时序收敛流程整合了增强型物理综合优化，提供了最佳的时钟布局、更好的封装和时序收敛映射，从而获得了更高质量的结果。

最佳布线算法能够有效地利用 65nm ExpressFabric™ 的对角对称互联，从而将延迟降至最低水平，和充分利用 Virtex-5 平台的高性能特性。 根据时序要求，ISE 9.1i 布线算法还支持引脚交换，从而可以将设计性能进一步最大化。

整个 ISE 9.1i 基础设施是一个扩展的时序收敛环境 - 虚拟“时序收敛平台（Timing Closure Cockpit）” - 实现了约束输入、时序分析、布局规划和报告窗口之间的无缝交叉探测，因此设计者能够更轻松的完成时序问题分析。

生产率

推出了新 SmartCompile 技术

映射、布局和布线算法的改善能够让用户将棘手的设计的编译次数平均加快2.5倍。 这让用户能够从他们的设计中获得更多的实现或回报，从而加快了面市，并减少了失败。

利用 ISE 9.1i 内的新 SmartCompile 技术，FPGA 设计者可以将运行时间平均加快 2.5 倍，而某些设计甚至可以将运行时间加快 6 倍。

SmartCompile 由 3 种新特性组成：SmartGuide、分区和 SmartPreview。

分区可以保证保留现有实现。 用户可以在其设计中定义分区或分级模块。 他们能够规定重新实现过程中要保留这些分区的综合、布局和/或布线。

SmartGuide 将相同设计不同版本之间的实现差异降至最低水平。 SmartGuide 由 ISE 项目浏览器（Project Navigator）提供，并且无需对现有设计流程做大量修改。可以加快运行时间，并且还能为不在关键路径上的小的设计修改保留时序。

SmartPreview 允许用户暂停和恢复实现。 这使得用户能够保存中间结果，查看设计状态（时序失败的路径、布线状态），生成比特流，并进行时序分析。 通过研究实现过程，这可以降低长实现周期的影响。

ISE 9.1i 包含其它一些有助于设计者快速实现时序收敛的新性能，包括：

*新的 Tcl 命令窗口：新的 Tcl 窗口让用户能够在 ISE 图形环境和命令行之间轻松实现导航。

*源代码控制性能：使得用户能够快速而又轻松地识别与其设计的已知版本相关的文件。 然后，他们可以导出重新生成具有*相同源和设置的项目所需的源文件与脚本。

*集成式时序收敛环境：在 ISE 9.1i 中对集成式时序收敛环境进行了扩展。 PACE、时序分析器、约束编辑器和布局规划器窗口的整合实现了这些窗口与 ISE 设计总结之间的交叉探测。 这使得用户能够从多个角度研究其设计和地址问题。 集成式时序收敛环境可用于 Virtex-5、Virtex-4 和 Spartan™-3A 器件。

功耗

动态功耗平均降低 10%

*先进的综合和实现算法将动态功耗降低了10%

*免费的、可下载的、领先的 Xilinx FPGA 的 XPower 估计器电子数据表让用户能够利用器件专用电子数据表工具快速而轻松地估计其项目的功耗。

*XPower 分析器包含 ISE 的所有配置，可以执行详细的基于设计的功耗分析，包括导入详细的设计精度方面的仿真文件。

*在 Xilinx 功耗中心，找到与功耗有关的问题

Xilinx 9.1i Packs New Capabilities

For system designers, Moore’s Law is a gravy train. Every couple of years, you get more gates, more speed, less power consumption, and lower cost. For digital designers and tool developers, however, that gravy train is headed through the tunnel right at you. Every couple of years, you have more gates to design in less time, more complexity to overcome, and tougher verification problems. Your design tools are heavily impacted, too. The old synthesis and place-and-route runs that took a few minutes on an old 200MHz Windows 98 laptop are now running for 24 hours on the latest multi-core, memory-laden, tricked-out machines.

Xilinx’s latest software release goes straight at that problem, acknowledging that in this day of platform-based design, IP re-use, hardware/software verification, and high-speed serial I/O, the toughest FPGA design challenge for most people is still basic timing closure from RTL to bitstream. Xilinx’s new ISE 9.1i includes two major enhancements: “SmartCompile,” to address timing closure on large designs, and some new power optimization capabilities to address the growing sensitivity to power consumption in today’s more FPGA-centric systems.

Xilinx tackled the runtime and productivity issue both in evolutionary progress on runtimes and algorithm efficiency (boosted by faster computing platforms, of course) and in more revolutionary change in the form of incremental design capability.

Before tackling incrementality, Xilinx claims to have achieved a 2.5X average improvement in runtime. Since we here in Journal land always hate “2.5X faster” as a way of talking about runtime improvements – here is what that means, according to our super-secret “execution speed” decoder ring: the runtime would be divided by 2.5, giving a 60% runtime reduction. Xilinx measures runtime over a suite of 100 “typical” customer designs on the same machine running the old and new versions of the software, then averages the deltas. Voila! 60% runtime reduction on average – “2.5X faster” (Ain’t marketing wonderful?) Actually, a 60% reduction is monumental in software performance tuning… particularly on a product whose release number is in the 9.X range. Normally, the easy speed gains are back in releases 1.x, 2.x etc. when you’ve got plenty of stupid n-squared loop issues to clean up. Mature software has much less low-hanging fruit.

Since most design (particularly the timing closure phase) involves iterative running of steps like synthesis and place-and-route, efficient, intelligent incremental design tools can effect a dramatic improvement in average iteration time. If you go into your design and change only one small section, you don’t want to wait around while all the other parts of your design are re-compiled exactly as they were before. You’d like for just the new and changed sections to require recompilation.

All this incrementality sounds great in concept, of course. It’s in the real-world implementation that problems crop up. That’s where Xilinx has had to focus their energy in providing practical incremental design. The classic difficulties in incremental compilation include things like sub-optimal timing results caused by modified parts of the design introducing new critical timing paths, some of which could benefit from a re-placement or re-synthesis of untouched design blocks. Additionally, sometimes you have to rip up or move existing sections of a design to make way for the new, larger, or otherwise different modified sections. Managing this squishy situation is one of the core challenges of incremental design tools. Another challenge is overhead management. Often, the compute and storage overhead required to provide incremental design capability can cause slowdowns and inefficiencies that eat up the speed gains that incrementality is intended to provide.

Xilinx claims to have addressed these issues in developing their new “SmartCompile” technology. When you’ve already run your design once, you can make minor changes without requiring the software to do a complete re-implementation of the design from scratch. Besides improving runtimes, this locks down the timing on parts of the design where you’ve already completed timing closure – the old non-incremental process could sometimes blow the results from one section of the design while processing changes in another. Preserving the old results as much as possible between incremental iterations helps speed convergence. Overall, Xilinx claims another “2.5X speedup” from incrementality on subsequent runs. By our decoder-ring math again – that means that you might save an average of 84% runtime on an incremental run with the new release versus a full run with the old release. Xilinx calls this a “6.25X faster” runtime.

Xilinx has also added a feature called “SmartPreview” that allows place-and-route to “pause” and “resume” – this allows you to view intermediate results without waiting for the whole run – a big time saver if you discover something that’s wrong early on instead of waiting for an overnighter to complete. The SmartPreview allows you to create a bitstream to take into a part immediately for debug, preserve your latest results as a snapshot, abort the place-and-route process entirely, or move to the next run of a multi-pass place-and-route process.

Finally, the new “SmartCompile” boasts a feature called “SmartGuide” that attempts to minimize the change between iterations, reducing the timing perturbation and runtimes for small design changes of the type usually encountered late in the design cycle. SmartGuide is a pushbutton algorithm that compares the new and old versions of a design, uses the original design as a guide, and incrementally places the new or changed elements and critical elements. It then identifies critical timing paths and incrementally routes new and critical paths to meet timing in order to reach a final implementation. Furthermore, you can manually identify partitions if you want to exercise more control, which is particularly useful for situations like team-based design where multiple engineers may be working on a single FPGA and be at different phases of their own implementation.

Xilinx has thrown a few more convenience and productivity features into the release, including a TcL console to allow scripting, the hooks necessary to integrate a variety of source code management systems into your design flow with ISE, and an expanded timing closure environment that brings together the various timing closure tools into one user interface.

The second major challenge tackled by the new ISE is power optimization. Power in FPGA designs is only recently becoming a first-class concern. Old FPGA users just took whatever power consumption they got, plugged in bigger power supplies and fans if needed, and took it all as an excuse for the occasional marshmallow roast over their development boards. Today, however, many designers actually care how much power their FPGA design will burn. FPGAs are becoming more central to the system, larger, and faster. All of those factors make them higher on the most-scrutinized components list for suspicion of power mongering.

First on Xilinx’s list of chores was to improve the accuracy and timeliness of power estimation. Many design projects have ended up far down the implementation trail only to discover that they were impossibly far over their power budget. Early estimation is the only way to get confidence that you’re headed toward a workable solution from a power perspective. Xilinx has included new power estimation spreadsheets into ISE that help you get a rough idea of the power picture early on.

Once you get into your design process, you want to cut power consumption as much as possible. Xilinx has added new power optimization in both synthesis and place-and-route that they claim automatically reduces dynamic power by an average of 10%. Power consumption is highly design- and stimulus-dependent, however, so don’t be surprised if you see a wide variation in your results.