词条 | 超高频多速开关电容电路设计(影印版) |
释义 | 本书以具体实例为依托,详细阐述了作者所设计的一款性能优越、用途广泛的高频开关电容电路,并对该电路设计中所涉及的模拟CMOS集成电路设计的很多重要问题进行讲解。而这些问题并不仅限于该书所介绍的电路类型,而是在模拟集成电路设计中经常会遇到的一些典型问题,所以本书的参考价值可以扩展到更大的领域。更难能可贵的是作者所设计的这款电路的优越性能得到了实际芯片测试的验证,增加了本书的权威性。 书名:超高频多速开关电容电路设计(影印版) 作者:潘森等 ISBN:10位[7030182499]13位[9787030182494] 页数:227 定价:¥35.00元 (根据地区不通价格不同) 出版社:科学 出版时间:2007-01 装帧:平装 开本:16开 目录Preface Acknowledgment ListofAbbreviations ListofFigures ListofTables 1INTRODUCTION 1.High-FrequencyIntegratedAnalogFiltering 2.MultirateSwitched-CapacitorCircuitTechniques 3.Sampled-DataInterpolationTechniques 4.ResearchGoalsandDesignChallenges 2IMPROVEDMULTIRATEPOLYPHASE-BASEDINTERPOLATIONSTRUCTURES 1.Introduction 2.ConventionalandImprovedAnalogInterpolation 3.PolyphaseStructuresforOptimum-classImprovedAnalogInterpolation 4.MultirateADBPolyphaseStructures 4.1CanonicandNon-CanonicADBRealizations 4.2SCCircuitArchitectures 5.Low-SensitivityMultirateIIRStructures 5.1MixedCascade/ParallelForm 5.2Extra-RippleIIRForm 6.Summary 3PRACTICALMULTIRATESCCIRCUITDESIGNCONSIDERATIONS 1.Introduction 2.PowerConsumptionAnalysis 3.Capacitor-RatioSensitivityAnalysis 3.1FIRStructure 3.2IIRStructure 4.FiniteGain&BandwidthEffects 5.Input-ReferredOffsetEffects 6.PhaseTiming-MismatchEffects 6.1PeriodicFixedTiming-SkewEffect 6.2RandomTiming-JitterEffects 7.NoiseAnalysis 8.Summary 4GAIN-ANDOFFSET-COMPENSATIONFORMULTIRATESCCIRCUITS 1.Introduction 2.AutozeroingandCorrelated-DoubleSamplingTechniques 3.AZandCDSSCDelayBlockswithMismatch-FreeProperty 3.1SCDelayBlockArchitectures 3.2GainandOffsetErrors-ExpressionsandSimulationVerification 3.3Multi-UnitDelayImplementations 4.AZandCDSSCAccumulators 4.1SCAccumulatorArchitectures 4.2GainandOffsetErrors-ExpressionsandSimulationVerification 5.DesignExamples 6.SpeedandPowerConsiderations 7.Summary 5DESIGNOFA108MHzMULTISTAGESCVIDEOINTERPOLATINGFILTER 1.Introduction 2.OptimumArchitectureDesign 2.1MultistagePolyphaseStructurewithHalf-BandFiltering.. 2.2Spread-ReductionScheme 2.3Coefficient-SharingTechniques 3.CircuitDesign 3.1lst-Stage 3.22nd-and3rd-Stage 3.3DigitalClockPhaseGeneration 4.CircuitLayout 5.SimulationResults 5.1BehavioraISimulations 5.2Circuit-LevelSimulations 6.Summary 6DESIGNOFA320MHZFREQUENCY-TRANSLATEDSCBANDPASSINTERPOLATINGFILTER 1.Introduction 2.PrototypeSystem-LevelDesign 2.1Multi-notchFIRTransferFunction 2.2Time-InterleavedSerialADBPolyphaseStructurewith Autozeroing 3.PrototypeCircuit-LevelDesign 3.1AutozeroingADBandAccumulator 3.2High-SpeedMultiplexer 3.3OverallSCCircuitArchitecture 3.4TelescopicopampwithWide-SwingBiasing 3.5nMOSSwitches136 3.6NoiseCalculation 3.7I/0Circuitry 3.8LowTiming-SkewClockGeneration 4.LayoutConsiderations 4.1DeviceandPathMatching 4.2SubstrateandSupplyNoiseDecoupling 4.3Shielding 4.4FloorPlan 5.SimulationResults 5.1OpampSimulations 5.2FilterBehavioralSimulations 5.3FilterTransistor-LevelandPost-LayoutSimulations 6.Summary 7EXPERIMENTALRESULTS 1.Introduction 2.PCBDesign 2.1FloorPlan 2.2PowerSuppliesandDecoupling 2.3BiasingCurrents 2.4InputandOutputNetwork 3.MeasurementSetupandResults 3.1FrequencyResponse 3.2Time-DomainSignalWaveforms 3.3One-ToneSignalSpectrum 3.4Two-ToneIntermodulationDistortion 3.5THDandIM3vs.InputSignalLevel 3.6NoisePerformance 3.7CMRRandPSRR 4.Summary 8CONCLUSIONS APPENDIX1TIMING-MISMATCHERRORSWITHNONUNIFORMLYHOLDINGEFFECTS 1.SpectrumExpressionsforIU-ON(SH)andIN-CON(SH) 1.1IU-ON(SH) 1.2IN-CON(SH) 2.ClosedFormSINADExpressionforIU-ON(SH)andIN-CON(SH) 2.1IU-ON(SH) 2.2IN-CON(SH) 3.ClosedFormSFDRExpressionforIN-CON(SH)systems 4.SpectrumCorrelationofIN-OU(IS)andIU-ON(SH) APPENDIX2NOISEANALYSISFORSCADBDELAYLINEANDPOLYPHASESUBFILTERS 1.OutputNoiseofADBDelayLine 2.OutputNoiseofPolyphaseSubfilters 2.1UsingTSIInputCoefficientSCBranches 2.2UsingOFRInputCoefficientSCBranches APPENDIX3GAIN,PHASEANDOFFSETERRORSFORGOCMFSCDELAYCIRCUITIANDJ 1.GOCMFSCDelayCircuitI 2.GOCMFSCDelayCircuitJ |
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