简介

指令集

支持SSSE3指令集的处理器

新增的指令

简介

SSSE3 （S

upplemental Streaming SIMD Extensions 3）是 Intel 命名的 SSE3 指令集的扩充，不使用新的号码是因为 SSSE3 只是加强版的 SSE3，以至于推出 SSSE3 之前，SSE4 的定义容易被混淆。在公开 Intel 的 Core 微架构的时候，SSSE3 于2006年7月首次装载在 Xeon 5100 与 Intel Core 2 行动版与桌面型处理器上。

指令集

SSE3装载了用一个命令一口气处理复数个数据的“SIMD”的处理方式，特别在处理语音和动画关联上能够高速地发挥力量。SSSE3是在SSE3命令的基础上又添加了32个新命令的产品，其原名为TNI，是SSE4指令集的子集,包含有13条命令。目前SSSE3也是比较先进的指令集。

SSSE3 包含了 16 个新的不同于 SSE3 的指令。每一个都能够运作于 64 位元的 MMX 暂存器或是 128 位元 XMM 暂存器之中。因此，有些 Intel 的文件表示有 32 个新指令。之前的 SIMD 指令由旧排到新依序是 MMX、3DNow!（AMD 开发的）、SSE、3DNow! Professional、SSE2与SSE3。

还没有确定正式名称为SSSE3的时候，其编码名称为TNI，被预测正式名称为“SSE4”，但结果被定为SSSE3，SSE4预定被使用于下一代微处理器中。

SSSE3指令集增强了CPU的多媒体、图形图象处理、多媒体编码、整数运算和Internet等方面的处理能力。

支持SSSE3指令集的处理器

Intel：

Xeon 5100 系列

Xeon 5300 系列

Xeon 3000 系列

Core 2 Duo

Core 2 Extreme

Core 2 Quad

Core i7

Core i5

Pentium Dual-Core

Celeron 4xx 的 Conroe-L

Celeron Dual Core 系列

Celeron M 500 系列

Atom

VIA：

Nano

新增的指令

In the table below, satsw(X) (read as 'saturate to signed word')takes a signed integer X, and converts it to -32768 if it's less than-32768, to +32767 if it's greater than 32767, and leaves it unchangedotherwise. As normal for the Intel architecture, bytes are 8 bits,words 16 bits, and dwords 32 bits; 'register' refers to an MMX or XMMvector register.

PSIGNB, PSIGNW, PSIGND　Packed Sign　Negate the elements of a register of bytes, words or dwords if thesign of the corresponding elements of another register is negative.

PABSB, PABSW, PABSD　Packed Absolute Value　Fill the elements of a register of bytes, words or dwords with the absolute values of the elements of another register

PALIGNR　Packed Align Right　take two registers, concatenate their values, and pull out aregister-length section from an offset given by an immediate valueencoded in the instruction.

PSHUFB　Packed Shuffle Bytes　takes registers of bytes A = [a0 a1 a2 ...] and B = [b0 b1 b2 ...] and replaces A with [ab0 ab1 ab2 ...]; except that it replaces the ith entry with 0 if the top bit of bi is set.

PMULHRSW　Packed Multiply High with Round and Scale　treat the sixteen-bit words in registers A and B as signed 15-bitfixed-point numbers between -1 and 1 (eg 0x4000 is treated as 0.5 and0xa000 as -0.75), and multiply them together with correct rounding.

PMADDUBSW　Multiply and Add Packed Signed and Unsigned Bytes　Take the bytes in registers A and B, multiply them together, addpairs, signed-saturate and store. IE [a0 a1 a2 ...] pmaddubsw [b0 b1 b2...] = [satsw(a0b0+a1b1) satsw(a2b2+a3b3) ...]

PHSUBW, PHSUBD　Packed Horizontal Subtract (Words or Doublewords)　takes registers A = [a0 a1 a2 ...] and B = [b0 b1 b2 ...] and outputs [a0-a1 a2-a3 ... b0-b1 b2-b3 ...]

PHSUBSW　Packed Horizontal Subtract and Saturate Words　like PHSUBW, but outputs [satsw(a0-a1) satsw(a2-a3) ... satsw(b0-b1) satsw(b2-b3) ...]

PHADDW, PHADDD　Packed Horizontal Add (Words or Doublewords)　takes registers A = [a0 a1 a2 ...] and B = [b0 b1 b2 ...] and outputs [a0+a1 a2+a3 ... b0+b1 b2+b3 ...]

PHADDSW　Packed Horizontal Add and Saturate Words　like PHADDW, but outputs [satsw(a0+a1) satsw(a2+a3) ... satsw(b0+b1) satsw(b2+b3) ...]