| 词条 | 逻辑与计算机设计基础 |
| 释义 | 逻辑与计算机设计基础从当代工程观点讲述了逻辑与计算机设计方面的内容，自出版以来已被全球超过25万人使用。本书以清晰的解释和逐步延伸的实例来帮助读者理解内容，实例涵盖了从简单的组合应用到建立在RISC内核基础上的CISC结构，更加重视培养读者在计算机辅助设计、问题形式化、解决方案验证和问题解决技巧方面的能力。 图书信息书 名:逻辑与计算机设计基础 作 者：（美）马诺，凯姆 出版社： 机械工业出版社 出版时间： 2010-4-1 ISBN: 9787111303107 开本： 16开 定价: 58.00元 内容简介本版更新内容 ·新增60个实例和习题。 ·新增和修改了40%的习题。 ·重新调整和组织了内容以适应不同的课程大纲。 ·技术内容的更新包括： 简要介绍嵌入式系统。 使用Espresso对实用的计算机辅助逻辑优化方法进行说明。 简要介绍MOS晶体管和CMOS电路。 补充了异步交互、同步和亚稳态相关知识。 一种新的控制单元和寄存器传输控制设计的图形表示。 更新了CRT显示和液晶屏显示的例子。 包括多核处理器的新型体系结构。 图书目录Preface Chapter 1 DIGITAL SYSTEMS AND INFORMATION 1-1 Information Representation The Digital Computer Beyond the Computer More on the Generic Computer 1-2 Number Systems Binary Numbers Octal and Hexadecimal Numbers Number Ranges 1-3 Arithmetic Operations Conversion from Decimal to Other Bases 1-4 Decimal Codes BCD Addition 1-5 Alphanumeric Codes ASCII Character Code Parity Bit 1-6 Gray Codes 1-7 Chapter Summary References Problems Chapter 2 COMBINATIONAL LOGIC CIRCUITS 2-1 Binary Logic and Gates Binary Logic Logic Gates 2-2 Boolean Algebra Basic Identities of Boolean Algebra Algebraic Manipulation Complement of a Function 2-3 Standard Forms Minterms and Maxterms Sum of Products Product of Sums 2-4 Two-Level Circuit Optimization Cost Criteria Map Structures Two-Variable Maps Three-Variable Maps 2-5 Map Manipulation Essential Prime Implicants Nonessential Prime Implicants Product-of-Sums Optimization Don't-Care Conditions 2-6 Pragmatic Two-Level Optimization 2-7 Multiple-Level Circuit Optimization 2-8 Other Gate Types 2-9 Exclusive-OR Operator and Gates Odd Function 2-10 High-Impedance Outputs 2-11 Chapter Summary References Problems Chapter 3 COMBINATIONAL LOGIC DESIGN 3-1 Design Procedure 3-2 Beginning Hierarchical Design 3-3 Technology Mapping 3-4 Verification Manual Logic Analysis Simulation 3-5 Combinational Functional Blocks 3-6 Rudimentary Logic Functions Value-Fixing, Transferring, and Inverting Multiple-Bit Functions Enabling 3-7 Decoding Decoder and Enabling Combinations Decoder-Based Combinational Circuits 3-8 Encoding Priority Encoder Encoder Expansion 3-9 Selecting Multiplexers Multiplexer-Based Combinational Circuits 3-10 Chapter Summary References Problems Chapter 4 ARITHMETIC FUNCTIONS AND I'-IDEs 4-1 Iterative Combinational Circuits 4-2 Binary Adders Half Adder Full Adder Binary Ripple Carry Adder 4-3 Binary Subtraction Complements Subtraction Using 2s Complement 44 Binary Adder-Subtractors Signed Binary Numbers Signed Binary Addition and Subtraction Overflow 4-5 Other Arithmetic Functions Contraction Incrementing Decrementing Multiplication by Constants Division by Constants Zero Fill and Extension 4-6 Hardware Description Languages Hardware Description Languages Logic Synthesis 4-7 HDL Representations-VHDL Behavioral Description 4-8 HDL Representations-Verilog Behavioral Description 4-9 Chapter Summary References Problems Chapter 5 SEQUENTIAL CIRCUITS 5-1 Sequential Circuit Definitions 5-2 Latches SR and S R Latches D Latch 5-3 Flip-Flops Master-Slave Flip-Flops Edge-Triggered Flip-Flop Standard Graphics Symbols Direct Inputs 5-4 Sequential Circuit Analysis Input Equations State Table State Diagram Sequential Circuit Simulation 54 Sequential Circuit Design Design Procedure Finding State Diagrams and State Tables State Assitmment Designing with D Flip-Flops Designing with Unused States Verification 5-6 Other Flip-Flop Types JK and T Flip-Flops 5-7 State-Machine Diagrams and Applications State-Machine Diagram Model Constraints on Input Conditions Design Applications Using State-Machine Diagrams 5-8 HDL Representafon for Sequential Circuits-VHDL 5-9 HDL Representation for Sequential Circuits-Verilog 5-10 Chapter Summary References Problems Chapter 6 SELECTED DESIGN TOPICS 6-1 The Design Space Integrated Circuits CMOS Circuit Technology Technology Parameters 6-2 Gate Propagation Delay 6-3 Flip-Flop Timing 6-4 Sequential Circuit Timing 6-5 Asynchronous Interactions 6-6 Synchronization and Metastability 6-7 Synchronous Circuit Pitfalls 6-8 Programmable Implementation Technologies Read-Only Memory Programmable Logic Array Programmable Array Logic Devices 6-9 Chapter Summary References Problems Chapter 7 REGISTERS AND REGISTER TRANSFERS 7-1 Registers and Load Enable Register with Parallel Load 7-2 Register Transfers 7-3 Register Transfer Operations 7-4 A Note for VHDL and Verilog Users Only 7-5 Microoperations Arithmetic Microoperations Logic Microoperations Shift Microoperations 7-6 Microoperations on a Single Register Multiplexer-Based Transfers Shift Registers Ripple Counter Synchronous Binary Counters Other Counters 7-7 Register-Cell Design 7-8 Multiplexer and Bus-Based Transfers for Multiple Registers Three-State Bus 7-9 Serial Transfer and Microoperations Serial Addition 7-10 Control of Register Transfers Design Procedure 7-11 HDL Representation for Shift Registers and Counters-VHDL 7-12 HDL Representation for Shift Registers and Counters-Verilog 7-13 Microprogrammed Control 7-14 Chapter Summary References Problems Chapter 8 MEMORY BASICS 8-1 Memory Definitions 8-2 Random-Access Memory Write and Read Operations Timing Waveforms Properties of Memory 8-3 SRAM Integrated Circuits Coincident Selection 8-4 Array of SRAM ICs 8-5 DRAM ICs DRAM Cell DRAM Bit Slice 8-6 DRAM Types Synchronous DRAM (SDRAM) Double-Data-Rate SDRAM (DDR SDRAM) RAMBUS DRAM (RDRAM) 8-7 Arrays of Dynamic RAM ICs 8-8 Chapter Summary References Problems Chapter 9 COMPUTER DESIGN BASICS 9-1 Introduction 9-2 Datapaths 9-3 The Arithmetic/Logic Unit Arithmetic Circuit Logic Circuit Arithmetic/Logic Unit 9-4 The Shifter Barrel Shifter 9-5 Datapath Representation 9-6 The Control Word 9-7 A Simple Computer Architecture Instruction Set Architecture Storage Resources Instruction Formats Instruction Specifications 9-8 Single-Cycle Hardwired Control Instruction Decoder Sample Instructions and Program Single-Cycle Computer Issues 9-9 Multiple-Cycle Hardwired Control Sequential Control Design 9-10 Chapter Summary References Problems Chapter 10 INSTRUCTION SET ARCHITECTURE 10-1 Computer Architecture Concepts Basic Computer Operation Cycle Register Set 10-2 Operand Addressing Three-Address Instructions Two-Address Instructions One-Address Instructions Zero-Address Instructions Addressing Architectures 10-3 Addressing Modes Implied Mode Immediate Mode Register and Register-Indirect Modes Direct Addressing Mode Indirect Addressing Mode Relative Addressing Mode Indexed Addressing Mode Summary of Addressing Modes 10-4 Instruction Set Architectures 10-5 Data-Transfer Instructions Stack Instructions Independent versus Memory-Mapped I/O 10-6 Data-Manipulation Instructions Arithmetic Instructions Logical and Bit-Manipulation Instructions Shift Instructions 10-7 Floating-Point Computations Arithmetic Operations Biased Exponent Standard Operand Format 10-8 Program Control Instructions Conditional Branch Instructions Procedure Call and Return Instructions 10-9 Program Interrupt Types of Interrupts Processing External Interrupts 10-10 Chapter Summary References Problems Chapter 11 RISC AND CISC CENTRAL PROCESSING UNITS 11-1 Pipelined Datapath Execution of Pipeline Microoperations 11-2 Pipelined Control Pipeline Programming and Performance 11-3 The Reduced Instruction Set Computer Instruction Set Architecture Addressing Modes Datapath Organization Control Organization Data Hazards Control Hazards 11-4 The Complex Instruction Set Computer ISA Modifications Datapath Modifications Control Unit Modifications Microprogrammed Control Microprograms for Complex Instructions 11-5 More on Design Advanced CPU Concepts Recent Architectural Innovations 11-6 Chapter Summary References Problems Chapter 12 INPUT-OUTPUT AND COMMUNICATION 12-1 Computer UO 12-2 Sample Peripherals Keyboard Hard Drive Liquid Crystal Display Screen I/O Transfer Rates 12-3 I/O Interfaces I/O Bus and Interface Unit Example of I/O Interface Strobing Handshaking 12-4 Serial Communication Synchronous Transmission The Keyboard Revisited A Packet-Based Serial I/O Bus 12-5 Modes of Transfer Example of Program-Controlled Transfer Interrupt-Initiated Transfer 12-6 Priority Interrupt Daisy Chain Priority Parallel Priority Hardware 12-7 Direct Memory Access DMA Controller DMA Transfer 12-8 Chapter Summary References Problems Chapter 13 MEMORY SYSTEMS 13-1 Memory Hierarchy 13-2 Locality of Reference 13-3 Cache Memory Cache Mappings Line Size Cache Loading Write Methods Integration of Concepts Instruction and Data Caches Multiple-Level Caches 13-4 Virtual Memory Page Tables Translation Lookaside Buffer Virtual Memory and Cache 13-5 Chapter Summary References Problems INDEX |
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