词条 | C/A码 |
释义 | GPS卫星发出的一种伪随机码 用于粗测距和捕获GPS卫星 它由2个10级反馈移位寄存器构成的G码产生。2个移位寄存器在每周日子夜零时,在置“1”脉冲作用下全处于1状态,同时在码率1.023MHZ下,2个移位寄存器分别产生码长为N=2^10-1=1023,周期为1ms的2个M序列G1(t)和G2(t)。G2(t)序列经过相位选择器,输入一个与G2(t)平移等价的M序列,然后与G1(t)模二相加,得到C/A码. C/A码的码元宽度较大。假设两个序列的码元对其误差为码宽的1/10~1/100,则此时相应的测距误差为29.3~2.93m。随着现代科学技术的发展,使得测距分辨率大大提高。一般最简单的导航接收机的伪距测量分辨率达到0.1m。 GPS系统中P码的捕获通常是利用C/A码来完成的,用户首先捕获到C/A码,然后利用C/A码调制的导航电文中的握手字(HOW-handover word)所提供的P码信息对P码进行捕获。由于P码在战争中显得十分重要,而且C/A码在民用中也发挥了很重要的作用,所以研究并实现C/A码具有一定的实际价值。 c/a 码发生器的FPGA实现代码: library ieee; use ieee.std_logic_1164.all; entity LFSR_A is generic(cycleA0:integer:=26; cycleA3:integer:=4; width:integer:=1); port( Clk:in std_logic; Enable:in std_logic; Fill_En:in std_logic; New_Fill:in std_logic_vector(width -1 downto 0); DelayA0:out std_logic_vector(width -1 downto 0)); end LFSR_A; architecture LFSR_A_ARCH of LFSR_A is signal Date_In_A:STD_LOGIC_VECTOR(width -1 downto 0); signal DelayA3:STD_LOGIC_VECTOR(width -1 downto 0); signal DelayA0_int:STD_LOGIC_VECTOR(width -1 downto 0); type my_type is array(0 to cycleA0 -1) of std_logic_vector(width -1 downto 0); signal int_sigA0:my_type; type my_type2 is array (0 to cycleA3 -1) of std_logic_vector(width -1 downto 0); signal int_sigA3:my_type2; begin main:process(Clk) begin if Clk'event and Clk ='1' then if (Enable='1') then int_sigA0<=Date_In_A & int_sigA0(0 to cycleA0 -2); int_sigA3<=Date_In_A & int_sigA3(0 to cycleA3 -2); end if; if (Fill_En='0') then Date_In_A<=DelayA3 xor DelayA0_int; else Date_In_A<=New_Fill; end if; end if; end process main; delayA0_int<=int_sigA0(cycleA0 -1); delayA3<=int_sigA3(cycleA3 -1); delayA0<=delayA0_int; end LFSR_A_ARCH; library ieee; use ieee.std_logic_1164.all; entity LFSR_B is generic (cycleB0:integer:=26; cycleB20:integer:=21; width:integer:=1); port( Clk:in std_logic; Enable:in std_logic; Fill_En:in std_logic; New_Fill:in std_logic_vector(width -1 downto 0); DelayB0:out std_logic_vector(width -1 downto 0) ); end LFSR_B; architecture LFSR_B_ARCH of LFSR_B is signal Data_In_B:std_logic_vector(width -1 downto 0); signal DelayB20:std_logic_vector(width -1 downto 0); signal DelayB0_int:std_logic_vector(width -1 downto 0); type my_type is array (0 to cycleB0 -1) of std_logic_vector(width -1 downto 0); signal int_sigB0:my_type; type my_type2 is array(0 to cycleB20 -1) of std_logic_vector(width -1 downto 0); signal int_sigB20:my_type2; begin main:process(Clk) begin if Clk'event and Clk='1' then if (Enable='1') then int_sigB0<=Data_In_B & int_sigB0(0 to cycleB0 -2); int_sigB20<=Data_In_B & int_sigB20(0 to cycleB20 -2); end if; if (Fill_En='0') then Data_In_B<=DelayB20 xor DelayB0_int; else Data_In_B<=New_Fill; end if; end if; end process main; delayB0_int<=int_sigB0(cycleB0 -1); delayB20<=int_sigB20(cycleB20 -1); delayB0<=delayB0_int; end LFSR_B_ARCH; library ieee; use ieee.std_logic_1164.all; entity Gold_Code is generic (width:integer:=1); port( Clock:in std_logic; Enable:in std_logic; Fill_En_A:in std_logic; Fill_En_B:in std_logic; Rst:in std_logic; New_Fill_A:in std_logic_vector(width -1 downto 0); New_Fill_B:in std_logic_vector(width -1 downto 0); Gold_Code:out std_logic_vector(width -1 downto 0) ); end Gold_Code; architecture Gold_Code_Arch of Gold_Code is component LFSR_A port (Clk:in std_logic; Enable:in std_logic; Fill_En:in std_logic; New_Fill:in std_logic_vector(width -1 downto 0); delayA0:out std_logic_vector(width -1 downto 0)); end component; component LFSR_B port (Clk:in std_logic; Enable:in std_logic; Fill_En:in std_logic; New_Fill:in std_logic_vector(width -1 downto 0); delayB0:out std_logic_vector(width -1 downto 0)); end component; signal DelayA_top:std_logic_vector(width -1 downto 0); signal DelayB_top:std_logic_vector(width -1 downto 0); begin U0:LFSR_A port map (Clk=>Clock,Enable=>Enable, Fill_En=>Fill_En_A, New_Fill=>New_Fill_A, delayA0=>delayA_top); U1:LFSR_B port map (Clk=>Clock,Enable=>Enable, Fill_En=>Fill_En_B, New_Fill=>New_Fill_B, delayB0=>delayB_top); Gold_Code<=delayB_top xor delayA_top; end Gold_Code_Arch; |
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